Tsi fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 222
TSI FPGA
ARTM-831X Installation and Use (6806800M76E)
222
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2
9.5.2.9.4 Supplemental Test Pattern Compare Data Register
Addresses:
0x1204, SupplTstPatDataCmpDatReg0
0x1244, SupplTstPatDataCmpDatReg1
0x1284, SupplTstPatDataCmpDatReg2
Width: 16 bit
This register determines the data the received test pattern from the supplementary channel
are compared to for error counting.
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
9.5.2.9.5 Test Pattern, CRC and Disparity Error Counter Control Register
Addresses:
0x1206, ErrCntCtrlReg0
0x1246, ErrCntCtrlReg1
0x1286, ErrCntCtrlReg2
Width: 8 bit
Bit
Acronym
Type
Description
Default
Pwr
Soft
15..
.0
SupplTstPatRcvData
R
Received pattern data.
undef
-
-
Bit
Acronym
Type
Description
Default
Pwr
Soft
15..
.0
SupplTstPatCmpDat
a
RW
compare pattern data.
0x0
X
X