Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 307)

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ARTM-831X Installation and Use (6806800M76E) 307
The bits of this register mask the bits of the CompEvtReg for the generation of Interrupt (MSI)
to the host via PCIE.
10.4.2.1.8 Xrt86 Framer Line Event Status Register
Address:
0x20, Xrt86LineEvtReg
Width: 32 bit
Bit Acronym Type Description Default Pwr Soft
7...5 - - reserved undef - -
4 Xrt86FramerAlrmMask RW 0b1:
Xrt86FramerAlrmEnable,
enables CompEvtReg Xrt86
framer alarm interrupt 0b0 X X
3 Xrt75LiuAlrmMask1 RW 0b1: Xrt75LiuAlrmEnable1,
enables CompEvtReg Xrt75
Liu alarm interrupt1 0b0 X X
2 Xrt75LiuAlrmMask0 RW 0b1: Xrt75LiuAlrmEnable0,
enables CompEvtReg Xrt75
Liu alarm interrupt0 0b0 X X
1 Xrt75LiuAlrmMask-1 RW 0b1: Xrt75LiuAlrmEnable-
1, enables CompEvtReg
Xrt75 Liu alarm interrupt-1 0b0 X X
0 Xrt75LiuAlrmMask-2 RW 0b1: Xrt75LiuAlrmEnable-
2, enables CompEvtReg
Xrt75 Liu alarm interrupt-2 0b0 X X