Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 146)

Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E) 146
8.3.1.25 FPGA Code SPI Update Registers
Table 8-50 FPGA Code SPI Control Register
Address: 0x1E
Bit Description Default Access
0 FPGA Code SPI Chip Select Control
1: Drive SPI Chip Select CONF_SPI_SS_ high
0: Drive SPI Chip Select CONF_SPI_SS_ low. 1 RTM r/w
5:1 Reserved 0 r
6 SPI Busy Bit:
0: Ready for next read or write access
1: Busy. The SPI clock is still toggling. 0 RTM: r
7 Enable FPGA Code Program Interface
0: Program Interface disabled. Bit 0 is always 1. Write to FPGA Code
SPI Data Register is ignored and read deliver 0.
1: Program Interface enabled. Chip Select is controlled by Bit 0 and
read and write accesses to FPGA Code SPI Data Register are
accepted. 0 RTM: r/w
Table 8-51 FPGA Code SPI Data Register
Address: 0x1F
Bit Description Default Access
7:0 FPGA Code SPI Write Data Register.
A write triggers 8 SPI clocks and shifts the data out to MOSI. The Data
on MISO is shifted in. - RTM: w
FPGA Code SPI Read Data Register.
Contains the data shifted in by the last write access to FPGA Code SPI
Data Register 0 RTM: r