Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 317)

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ARTM-831X Installation and Use (6806800M76E) 317
10.4.2.1.11Xrt75 Line Interface Line Event Register
Addresses:
0x30, Xrt75LineEvtReg0
0x40, Xrt75LineEvtReg1
0x50, Xrt75LineEvtReg2
0x60, Xrt75LineEvtReg3
Width: 32 bit
5 Xrt86Chp2RcvLoSIntrpt
Mask5 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable5,
enables chip 2 receiver Line 5 loss
of signal interrupt bit 0b0 X X
4 Xrt86Chp2RcvLoSIntrpt
Mask4 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable4,
enables chip 2 receiver Line 4 loss
of signal interrupt bit 0b0 X X
3 Xrt86Chp2RcvLoSIntrpt
Mask3 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable3,
enables chip 2 receiver Line 3 loss
of signal interrupt bit 0b0 X X
2 Xrt86Chp2RcvLoSIntrpt
Mask2 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable2,
enables chip 2 receiver Line 2 loss
of signal interrupt bit 0b0 X X
1 Xrt86Chp2RcvLoSIntrpt
Mask1 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable1,
enables chip 2 receiver Line 1 loss
of signal interrupt bit 0b0 X X
0 Xrt86Chp2RcvLoSIntrpt
Mask0 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable0,
enables chip 2 receiver Line 0 loss
of signal interrupt bit 0b0 X X
Bit Acronym Type Description Default Pwr Soft