Altera DDR Timing Wizard - Manual (Page 10)

1–4 Altera Corporation
DDR Timing Wizard User Guide November 2007
Introduction
1
Critical resynchronization register placement constraints
provided by the legacy controller MegaWizard can still be used
even when DTW is used. You can use LogicLock regions in lieu
of hard placement constraints.
1
The results reported by the dtw_timing_analysis.tcl script have
no correlation with the verify_timing.tcl script. You should rely
on the dtw_timing_analysis.tcl report, as it is more accurate
due to the design-specific constraints created by the DTW. The
verify_timing.tcl
script may have some assumption that does
not apply to your particular design.
To use the DTW, you must enter the memory device parameters and your
board information correctly in the legacy controller MegaWizard. The
Quartus II Fitter uses timing-driven compilation to route the design to
meet the timing constraints set by the DTW.
Because the DTW is primarily a constraining tool, the
dtw_timing_analysis.tcl
script is provided to help you analyze and close
timing with a minimum number of compilations. The
dtw_timing_analysis.tcl
script extracts the system timing margin by
re-running timing analysis if needed, adjusting the clock cycles in the
DTW (with the -auto_adjust_cycles switch) if required, and
suggesting the ideal phase shifts for the system. The
dtw_timing_analysis.tcl
is backwards-compatible with designs
constrained with an older version of DTW. Both DTW and the
dtw_timing_analysis.tcl
scripts are available in the Quartus II
installation directory.
1
If you use the default installation directory, the DTW and
dtw_timing_analysis.tcl
scripts are available in the
c:\altera\ <version>\quartus\common\tcl\apps\
gui\dtw directory.