Altera DDR Timing Wizard - Manual (Page 57)

Altera Corporation 2–45
November 2007 DDR Timing Wizard User Guide
Getting Started
After you click Finish, your project should have the following
assignments:
● DQS/DQ pin location, loading, and I/O standard assignments
from the legacy controller MegaWizard-generated script
● Timing constraints from the DTW
17. Add the additional assignments as listed on Step 4 of the “Design
Flow” section.
You are now ready to compile the design and perform timing
analysis.
The DTW Pages for QDRII+/QDRII SRAM & RLDRAM II
The steps for the QDRII+/QDRII SRAM or RLDRAM II interface are
similar to the steps for the DDR/DDR2 SDRAM interface. The following
is a summary:
1. From the Tools menu, select Tcl Scripts. Select DTW and click Run.
2. Specify a .dwz file name to save the timing constraints for the
design and click Next.
3. Confirm the project directory and revision you want to use and click
Next
.
4. On the Import page, click Next, then click Next again.
5. Select the memory type and device and click Next.
6. Specify your CQ pins (for QDRII+/QDRII SRAM) or QK pins for
(RLDRAM II) and click Next.
7. Specify the read data associated with each CQ and QK pins. For
QDRII+/QDRII SRAM, you must specify the QK# pins if you are
using it to capture data and click Next.
8. Specify the clocks to the memory and click Next.
9. Specify the write data and data mask pins associated with each
write clock and click Next.
10. Specify control and address pins and click Next.
11. Specify PLL outputs driving the memory clocks and the
resynchronization scheme and click Next.