Altera DDR Timing Wizard - Manual (Page 40)

2–28 Altera Corporation
DDR Timing Wizard User Guide November 2007
Entering and Editing Inputs to the DTW
f
Refer to AN 413: Using Legacy Integrated Static Data Path and
Controller Megafunction with HardCopy Structured ASICs on
how to generate CK/CK# signals using dedicated clock
outputs.
You then must enter the PLL input clock name and the multiplication
and division factors to achieve the memory interface frequency of
operation. In
Figure 2–19 , the design uses a 100-MHz input clock, so
the multiplication and division factors are set to 8 and 3, respectively,
to interface with a 267-MHz DDR2 SDRAM DIMM.
The name of the PLL output resynchronizing read data from the read
capture registers depends on whether you are using the 2-PLL mode
or the 1-PLL mode. The example design uses the 2-PLL mode, so the
PLL output resynchronizing read data from the read capture
registers that comes from the fedback PLL.
In 2-PLL mode, the DTW must know the clock cycle of the fedback
resynchronization clock and the system (second) resynchronization
clock. The legacy controller MegaWizard only provides the clock
cycle for the system resynchronization clock, so the DTW has to
calculate the fedback resynchronization clock cycle
(resync_cycle) in 2-PLL mode.
1
In 1-PLL mode, there is only one clock cycle information
required since there is only one resynchronization clock.
This clock cycle is also called resync_cycle and is
provided by the legacy controller MegaWizard.
Because the DTW must know the clock cycle and the clock phase
shift for each data transfer, there is a register transfer between the
fedback PLL resynchronization clock and the system PLL
resynchronization clock in 2-PLL mode interfaces. The legacy
controller MegaWizard only needs to know the clock cycle on the
system PLL side, so the DTW manually calculates this in 2-PLL
mode. The legacy controller MegaWizard provides this number in
1-PLL mode since there is only one resynchronization clock from the
system PLL in this implementation.
The resync_phase field should match the phase shift entered in
the legacy controller MegaWizard in the Fed-back clock phase field.
An example of the proper name for a PLL clock output for
resynchronization clock is shown in
Figure 2–20 . See Figure 2–21 for
matching each resynchronization field in the legacy controller
MegaWizard in the DTW.