Altera DDR Timing Wizard - Manual (Page 13)

Altera Corporation 2–1
November 2007
2. Getting Started
System and
Software
Requirements The instructions in this section require Quartus II software version 7.2 or
higher. DTW and the dtw_timing_analysis.tcl script can be found in the
Quartus II installation directory. You can either run the script from that
directory or copy the script to your project directory.
1
If you use the default installation directory, the DTW and
dtw_timing_analysis.tcl
script are available in the
c:\altera\ <version>\quartus\common\tcl\apps\
gui\dtw directory.
Design Flow The design flow when creating a system with external memory interfaces
is as follows:
1. Create a memory interface PHY with Altera’s legacy memory
controller MegaWizard.
f
For more information about how to create a memory
controller, refer to the
DDR & DDR2 SDRAM Controller
Compiler User Guide , QDRII SRAM Controller MegaCore ®
Function User Guide , and RLDRAM II Controller MegaCore
Function User Guide . Follow the instructions up to
generating the core, but do not compile the design yet.
f
To create an example design, follow the Instantiate PHY
and Controller in a Quartus II Project
step of the
"Example Walkthrough for 267-MHz DDR2 SDRAM
Interface using the Legacy PHY" section in
AN328:
Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and
Arria GX Devices
.
If you are not using the Altera memory controller, remove the
encrypted controller produced by the legacy controller MegaWizard
and connect the Altera-recommended data path from the legacy
controller MegaWizard with your memory controller.
2. Run the auto_add_ddr_constraints.tcl script produced by the
legacy controller MegaWizard for pin location, I/O standard,
output pin load, and register placement assignments for the
resynchronization and postamble registers in DDR2/DDR SDRAM
interfaces.