Altera DDR Timing Wizard - Manual (Page 35)

Altera Corporation 2–23
November 2007 DDR Timing Wizard User Guide
Getting Started
9. Identify the CK and CK# pins. The Altera DDR/DDR2 SDRAM
Controller uses clk_to_sdram and clk_to_sdram_n signal
names for CK and CK# pins, respectively, as shown in
Figure 2–17 .
Figure 2–17. Default CK & CK# Pin Names for the DDR/DDR2 SDRAM Controller
Click Next.