Altera DDR Timing Wizard - Manual (Page 52)

2–40 Altera Corporation
DDR Timing Wizard User Guide November 2007
Entering and Editing Inputs to the DTW
When you check the option to use Both fast and slow timing model
tcos
, DTW uses the fastest t
CO
from the fast model and slowest t
CO
from the slow model to generate constraints for resynchronization
and postamble paths. This means that you may be over-constraining
your design since both the fastest and slowest t
CO
s never occur
simultaneously. The advantage of the option is that the Quartus II
software analyzes timing for both fast and slow timing model
concurrently, and shows timing analysis results for both models in
the same compilation panel.
Using Slow timing model tco and Fast timing model tco separately
gives you more accurate timing constraints. If you want to use slow
and fast timing model separately, always check the Slow timing
model tcos
option as you must use the slow model timing
constraints for compilation. The dtw_timing_analysis.tcl will then
use the fast timing model t
CO
s to extract fast model timing margin for
the design, and then returns the DTW mode back to the slow timing
model t
CO
s.
Click Next.
16. The last page of the DTW lists the timing assignments that the DTW
applies to the project. The top dialog box in the page shows the
timing assignments made based on your inputs. For descriptions of
any of these assignments, highlight any of the assignments in the
top dialog box. The description of the highlighted assignment is
displayed in the Assignment Description dialog box.
The third dialog box reports the ideal data window for capture and
resynchronization. It also shows you how to check t
DQSS
, address,
command, and write timing manually. This dialog box also suggests
methods to close timing.
The last section of the page shows the name of the .sdc (and .tcl) files
that contain the assignments made by DTW, which should match the
.dwz
name that was chosen in the first page of DTW. When using
TimeQuest Timing Analyzer names, DTW generates an .sdc file that
contains timing constraints for both fast and slow timing models.
When using Classic Timing Analyzer names, DTW generates both a
.tcl
file (containing assignments that can be saved in the project’s .qsf
file) and an .sdc file (if you decide to compile the design using
TimeQuest Timing Analyzer later) if you choose to run the fast and
slow timing analysis concurrently, as shown in
Figure 2–28 . If you
choose to run the fast and slow timing analysis separately, DTW