Altera DDR Timing Wizard User Manual

Page 79

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Altera Corporation

3–19

November 2007

DDR Timing Wizard User Guide

Using the dtw_timing_analysis.tcl Script

Extract tcos

button in DTW or use the –extract_tco switch in the

dtw_timing_analysis.tcl

. You need to extract the CK/CK# t

CO

s manually

if you are using dedicated clock output for CK/CK# (as in designs
targeting HardCopy II devices). Also, if you did not lock down your pins,
your design's t

CO

s may vary from one compilation to another. These t

CO

numbers are used to calculate skew between output pins for your write
timing margin.

1

You do not need this step when using TimeQuest Timing
Analyzer as TimeQuest Timing Analyzer does not use skew to
calculate write timing margin. Instead, it uses set_output_delay
assignments.

Ensure the Changes Made Outside Legacy Controller
MegaWizard Are Not Erased When the Core is Regenerated

This is applicable to DDR2/DDR SDRAM, QDRII+/QDRII SRAM, and
RLDRAM II interfaces.

When you click Generate in the legacy controller MegaWizard, all RTL
and constraint files are regenerated. If you have made any changes to the
constraints or RTL files outside of the MegaWizard, these changes may be
reverted back to the initial MegaWizard settings. You can avoid this by
disabling some of the Project Settings options.

There are four options that you can set under the Example Design
Settings

in the legacy DDR2/DDR SDRAM controller MegaWizard:

1

There are only three options available in the legacy
QDRII+/QDR II SRAM and RLDRAM II controller
MegaWizard. These memory controllers do not have their own
timing analysis script.

1.

Automatically apply datapath-specific constraints to the Quartus II
project.

This setting runs the auto_add_ddr_constraints.tcl before the design
compilation. You should disable this if you are making any changes
to a compiled project where you had made changes to the constraints
to suit your actual board layout.

2.

Update the example design file that instantiates the controller
variation.

This setting updates the design example connections, if you had
made changes to the resynchronization or postamble connection.
However, if you had changed the RTL files previously to create a

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