Altera DDR Timing Wizard - Manual (Page 9)

Altera Corporation 1–3
November 2007 DDR Timing Wizard User Guide
About the DDR Timing Wizard
1
The new ALTMEMPHY megafunction, introduced in Quartus II
version 6.1 uses timing constraints generated by the
ALTMEMPHY MegaWizard, so that you do not need to use
DTW to constrain the design. DTW does not support
ALTMEMPHY-based memory controllers.
In addition to possible inaccurate assumptions of the design, placement
constraints did not work well for designs migrating to HardCopy II or
other FPGA devices. When migrating designs, especially to a HardCopy
II device, you would need two different sets of placement constraints: one
for the FPGA prototype device and one for the HardCopy production
device. This also applies when migrating designs to a different FPGA
device.
DDR Timing Wizard
The DDR Timing Wizard (DTW) is a Tcl-based GUI that calculates timing
constraints based on the FPGA and memory device chosen. It simplifies
the process of constraining your design by using timing assignments,
which the Quartus II software uses to place and route the design in the
target device. These timing constraints are applicable for FPGAs and their
HardCopy-equivalent devices, eliminating the need to convert
assignments for the different device families (as you would have
previously done with the placement constraints from legacy controller
MegaWizard). Some critical register placements can be constrained by
using LogicLock region assignments, but other than the pin location,
output pin load, and I/O standards assignments, you do not need any
hard placement constraints. Instead, the timing-driven compilation of the
Quartus II software ensures that all DTW timing constraints are met in
both FPGA-prototype and HardCopy-production devices.
DTW also gives you the ability to change the pin names of the memory
interface to use regional clock networks, and to use TimeQuest Timing
Analyzer to analyze the design, which are not supported by the
verify_timing.tcl
script. DTW constraints also lead to a more accurate
timing analysis, as all the information used are based on your particular
design, instead of general assumptions made by the MegaWizard.
Furthermore, the timing verification script does not report write timing
margin. DTW, on the other hand, constrains timing for the write path,
allowing Quartus II to analyze the write timing margin. You can then use
the dtw_timing_analysis.tcl script to report read, write,
address/command, resynchronization, and postamble timing margins
that are applicable to your memory interface design. DTW constraints
provide more accurate timing results compared to the verify_timing.tcl
script.