Altera DDR Timing Wizard - Manual (Page 61)

Altera Corporation 3–1
November 2007
3. Using the
dtw_timing_analysis.tcl
Script
Introduction If your design does not meet timing, you must know how to optimize the
design to meet all the timing requirements. DTW is a constraining tool;
however, it does not actually perform timing analysis or offer suggestions
on how to optimize the design.
The Quartus II compilation report lists the timing analysis results from
the timing constraints applied by the DTW. These are shown as setup and
hold margins on a per-pin basis for a given clock domain. You can use
this information to optimize the design, but manual timing margin
extraction and optimization is tedious as the optimization part requires
iterative compilation and phase shift adjustments.
The dtw_timing_analysis.tcl script extracts the margin for every pin and
displays the worst margin for each timing path with both fast and slow
timing models, and suggests the best phase shift selections for the
interface. This section describes how to use the dtw_timing_analysis.tcl
script to perform the required timing analysis and optimize designs with
memory interfaces.