Changing clock phase shift – Altera DDR Timing Wizard User Manual

Page 83

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Altera Corporation

3–23

November 2007

DDR Timing Wizard User Guide

Using the dtw_timing_analysis.tcl Script

For actual steps on how to change the phase shift, refer to

“Changing

Clock Phase Shift”

.

Changing Clock Phase Shift

This is applicable to DDR2/DDR SDRAM interfaces and RLDRAM II
interfaces. In RLDRAM II interfaces, this only applies for the
address/command clock setting.

After making sure that it is safe to change the clock phase shift for a
particular PLL output, you have two options to perform the change:

1.

Via the Legacy Controller MegaWizard

To change the resynchronization and postamble clock phase shifts in
DDR2/DDR SDRAM interfaces, go to the Manual Timings page of
the DDR2/DDR SDRAM Parameterize window.

To change the address/command clock phase shift in RLDRAM II
interfaces, go to the Timing page of the RLDRAM II Parameterize
window. You can choose either the falling or rising edge of the
system clock, write clock, or a dedicated PLL output clock. You can
also pick any phase shift when using the dedicated PLL output clock
for the address/command clock.

2.

Via the altpll MegaWizard

In DDR2/DDR SDRAM interfaces, if you do not need to change the
resynchronization or postamble or both clock cycles and you already
used dedicated PLL output for these clocks, you can simply change
the phase shift using the altpll MegaWizard for the PLL clock
output to be adjusted.

In RLDRAM II interfaces, peform the following:

a.

Determine which clock (system, write, or dedicated clock) you
need for this path.

If the Recommended Settings panel from the
dtw_timing_analysis.tcl

asks you to use a phase shift that is

closed to 0° or 180° clock, you can use the system clock with
positive and negative edge, respectively. Similarly if it asks you
to use a phase shift that is closed to 90° or 270° clock, use the
write clock, with either negative or positive edge, respectively.
If the phase shift recommended is not near to any of these phase
shift, you need a dedicated PLL output clock.

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