Altera DDR Timing Wizard - Manual (Page 59)

Altera Corporation 2–47
November 2007 DDR Timing Wizard User Guide
Getting Started
■ When using the DDR/DDR2 SDRAM core version 3.4.0 and
Quartus II version 6.0 or older with DQS hardware capture and a
fedback clock, the read resynchronization to the System PLL cycle is
imported from the IP, assuming it is normalized for a CAS 2
memory. It is actually normalized for a CAS 3 memory, so adjust the
read resynchronization cycle by +1 on the PLL Parameters page (see
Figure 2–19 on page 2–25 ).
■ When using the DDR/DDR2 SDRAM core version 3.4.0 with DQS
hardware capture and a fedback clock, the DTW may make poor
estimates for the first stage read resynchronization and postamble
cycles in the PLL parameters page (
Figure 2–19 on page 2–25 ). These
may need to be adjusted to line up the timing analysis for the second
stage read resynchronization and read postamble.
■ If you use the DQS hardware with the read postamble hardware, the
transfer of the postamble signal from the system (0°) clock to the read
postamble clock does not have an uncertainty assignment applied to
it. Manually apply the same uncertainty used for the DQS to
resynchronization clock transfer to the system clock to postamble
clock transfer.
■ The Node browse buttons can take some time to respond if your
design is a large one.
■ When using the Classic Timing Analyzer, the maximum data arrival
skew assignments cannot be translated into PrimeTime timing
assignments, as maximum data arrival skew is not a PrimeTime
defined assignment. If using the TimeQuest Timing Analyzer, the
output skew will be checked with set_output_delay constraints that
can be translated to PrimeTime.
■ You can ignore similar warnings as below that may occur when
updating timing netlist in TimeQuest:
Info: The source clock for this clock assignment cannot
be reached. Clock: clk_to_sdram[0] might not have valid
arrival time.
This is because TimeQuest tries to compute a generated clock’s
(clk_to_sdram[0] signal in this example) clock latency by finding
the base clock of the generated clock by tracing its inputs. In this case,
the generated clock is the feedback clock input pin, which does not
have any inputs to trace. The Info messages are noting this fact, and
the fact that it will have to rely entirely on the set_clock_latency
assignments on the feedback pin for its latency.