Figure 2–22, Show – Altera DDR Timing Wizard User Manual
Page 43
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Altera Corporation
2–31
November 2007
DDR Timing Wizard User Guide
Getting Started
Figure 2–22. Postamble Clock Connectivity
The postamble_sys_cycle and postamble_sys_phase are
specific to the fedback-clock mode implementation. The
postamble_sys_cycle
information should match with the
number in the legacy controller MegaWizard. The
postamble_sys_phase
, however, depends on whether the option
to use intermediate postamble registers is checked in the legacy
controller MegaWizard or not. When the option is checked,
postamble_sys_phase
is set to 0
°
. When the option is not checked
in the design, postamble_sys_phase is set to –180
°
.
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