Altera DDR Timing Wizard - Manual (Page 80)

3–20 Altera Corporation
DDR Timing Wizard User Guide November 2007
Timing Closure Process
dedicated PLL output for your address/command clock or to add
your own logic to the example design, disable this option so that the
MegaWizard does not overwrite your previous changes. If you
change any clock connections in the MegaWizard (such as the
postamble and resynchronization clock connections), you must
manually change the connection in the RTL files.
3. Automatically verify datapath-specific timing in the Quartus II
project.
This setting runs the verify_timing.tcl script that the MegaWizard
generates to check the timing of the interface. However, you should
use DTW to close timing. This setting needs to be disabled when you
generate the memory controller for the first time. This option is not
available in the QDRII+/QDRII SRAM and RLDRAM II memory
interfaces.
4. Update the example design PLL.
This setting updates any phase shift changes for the PLLs. Disable
this option if you had created a dedicated PLL output for your
address/command clock, or if you had added other PLL output
clocks for other parts of your design. You then need to manually
change the phase shift in the altpll MegaWizard.
1
In a 2-PLL mode interface, the fedback PLL always gets
updated even with this option off. This option only disables
PLL changes for the system PLL in these interfaces.
Figure 3–10 shows a modified Project Settings window where all
four settings are disabled. With these options off, any changes for
timing closure can be done manually in the RTL or altpll
MegaWizard, except:
● When you need to change the clock cycles of the
resynchronization or postamble clock.
● When you need to add or remove the intermediate registers for
the resynchronization or postamble path.
● When you need to add a dedicated clock for resynchronization,
postamble, or the address/command clock (if you have not
previously done so).