Altera DDR Timing Wizard - Manual (Page 16)

2–4 Altera Corporation
DDR Timing Wizard User Guide November 2007
Design Flow
standard as the CK/CK# pins, and are placed on the same side
as the DQS/DQ pins.
● Assign pin location, I/O standard, and output pin load
constraints for clock_source, feedback input pins, and
address and command pins.
● For RLDRAM II memory interfaces created in Quartus II
version 7.2 and higher, add the
<variation_name>_controller.sdc
file to the project
● For QDRII+/QDRII SRAM memory interfaces using TimeQuest
Timing Analyzer, convert the setup_relationship and
hold_relationship
MegaWizard-generated constraints to
SDC constraints. The setup_relationship and
hold_relationship
assignment can be directly converted to
set_max_delay and set_min_delay assignments, as shown
in the below example:
set_max_delay -0.2 -from * -to <resync_registers*>
set_min_delay -1.6 -from * -to <resync_registers*>
5. Compile the design.
6. Check the timing analysis results.
After completing a DTW design compilation, refer to Chapter 3,
Using the dtw_timing_analysis.tcl Script for information about
analyzing the memory interfaces.
If problem paths are reported, locate and fix them to maximize setup
and hold slack. For example, you can:
● Adjust PLL clock phases with the legacy controller or the
altpll
MegaWizard.
1
Note that some clock phases can only be changed in the
legacy controller MegaWizard, especially for shared PLL
outputs. For example, if your postamble clock was set to 90°
initially, but you want to change it to use either a dedicated
clock or a 180° phase shift.
● Insert or remove intermediate resynchronization and/or
postamble registers in the legacy controller MegaWizard.