Altera DDR Timing Wizard - Manual (Page 84)

3–24 Altera Corporation
DDR Timing Wizard User Guide November 2007
Timing Closure Process
b. Open the <project_name>.v/.vhd to check which clock is
currently used.
c. Look for the line:
assign addr_cmd_clk =
If the text on the right-hand side of the "=" sign is either clk or
write_clk
, currently the address/command clock is using the
system clock or write clock, respectively. You can change it to
!clk
or !write_clk, if you need the negative-edge version of
the clock. If you need to use a dedicated PLL output clock
instead, change that text to a different name (for example,
dedicated_addr_cmd_clk
).
1
Remember whether you selected the rising edge or the
falling edge for the address/command active clock edge.
If you are using a dedicated PLL output clock:
i. Search for the following line in the <project_name>.v/.vhd:
rldramii_pll_stratixii
This is the PLL module for the RLDRAM II interface. You
should see code similar to:
rldramii_pll_stratixii
g_stratixii_pll_rldramii_pll_inst
(
.areset (reset),
.c0 (clk),
.c1 (write_clk),
.c2 (addr_cmd_clk),
.c3 (memory_clk_0),
.c4 (memory_clk_1),
.c5 (memory_clk_2),
.inclk0 (clock_source),
.locked (pll_locked)
);
Ensure that the c2 output is connected to
dedicated_addr_ddr_cmd_clk
.