Altera DDR Timing Wizard - Manual (Page 58)

2–46 Altera Corporation
DDR Timing Wizard User Guide November 2007
DTW Limitations
1
You can use a similar resynchronization scheme like
DDR/DDR2 interfaces or use a FIFO to resynchronize the
data back to the system clocks. Altera RLDRAM II and
QDRII+/QDRII SRAM Controller MegaCore functions use
a FIFO for data resynchronization.
12. Specify the PLL output generating the write clocks and click Next.
13. Enter board skew information and click Next.
14. Verify the FPGA parameters page and click Next.
1
You can either use the default numbers or t
CO
s if you have
compiled the design.
1
All of the assignments made based on your inputs are
available on the final page.
15. Confirm the final page and click Finish.
16. Add the additional assignments as listed on Step 4 of “Design Flow”
on page 2–1 .
17. Compile the design.
DTW Limitations Limitations when using the DTW include:
■ Proper timing analysis of outputs (such as write data, data masks,
addresses, and commands) can only be performed with the
TimeQuest Timing Analyzer using the Synopsys design constraints
(SDC) file generated by the DTW. The SDC file is specified by the last
line on the last panel of the DTW (see
Figure 2–31 on page 2–44 ).
However, even if you are using the classic timing analyzer, the
dtw_timing_analysis.tcl
script will use TimeQuest Timing Analyzer
to analyze the timing of these outputs.
■ The SDC file currently only supports full-rate address/command
timing.
■ If you are using a custom QDRII+ SRAM interface, add the QVLD
pin as an additional read data pin. The current version of the Altera
QDRII+ SRAM controller MegaCore function does not support
QVLD pin.