Altera DDR Timing Wizard User Manual
Page 15
Altera Corporation
2–3
November 2007
DDR Timing Wizard User Guide
Getting Started
the names of the PLL clocks and registers (as needed) for the timing
requirements. It also extracts the phase shifts of synthesized PLLs.
The step-by-step instructions are listed in
Altera Legacy Memory Controller IP Core or Recommended Data
Path” on page 2–7
.
1
You may need to re-run DTW and compile the design
multiple times before achieving timing closure. You can
close timing within two compiles if you do not need to
change the intermediate registers option in the legacy
controller MegaWizard.
4.
Add other assignments for the design.
Add the following assignments in the Assignment Editor (unless
indicated otherwise) to the project before you compile the design:
●
If you are using classic Timing Analyzer:
•
In the Settings tab of the Assignment menu, uncheck the
Optimize hold timing
option.
•
In the Settings tab of the Assignment menu, uncheck the
Optimize fast corner timing
option.
This disallows the Quartus II Fitter from optimize placement
each time the project is recompiled. Having these options
enabled may render your phase shift changes invalid because
the Quartus II Fitter has the priority to optimize for hold timing
and fast cornering.
You can re-enable the Optimize hold timing and Optimize fast
corner timing
options for the remainder of the design after you
close timing on your memory interface. To ensure the memory
interface part of the design has similar timing, back-annotate
placements and routing for that portion of the design before re-
enabling the options.
●
If you are using TimeQuest Timing Analyzer, add the
DTW-generated .sdc file to the project.
●
Set the delay from Output Register to Output Pin to 0 for the
CK/CK# (clk_to_sdram*) clock outputs and fedback clock
output.
●
Assign pin constraints for all the CK/CK# and feedback output
pins and ensure that the feedback output pins use the same I/O