Altera DDR Timing Wizard - Manual (Page 17)

Altera Corporation 2–5
November 2007 DDR Timing Wizard User Guide
Getting Started
1
You need to insert intermediate resynchronization registers
when you have negative margin in the transfer between
resynchronization registers and the registers clocked by the
system clock. The dtw_timing_analysis.tcl script will tell
you when to add or remove the intermediate postamble
registers.
● Change the data path resynchronization and/or postamble
clock cycles in the legacy controller MegaWizard.
● Change location assignments to the problem PLL clocks, I/O
pins, or registers.
f
Refer to Chapter 3, Using the dtw_timing_analysis.tcl
Script for information on how to fix your timing violations
using the dtw_timing_analysis.tcl script.
1
If you need to change any PLL phase shifts, re-run the
Quartus II Analysis and Synthesis to refresh the PLL
settings before importing the new phase shift in the DTW.
You can click on the Start Analyze & Synthesis button
manually or use the –after_iptb import option in the
dtw_timing_analysis.tcl
script. You can also enter the PLL
phase shifts manually in the DTW to bypass Quartus II
Analysis and Synthesis. However, DTW will not be able to
confirm if the phase shift entered is the correct phase shift
that is implemented in the design.
If there are no failing paths, your design is complete. Otherwise, go
back to step
5 after making the necessary timing requirements
changes until the design achieves timing closure.
Launching the
DDR Timing
Wizard To launch the DDR Timing Wizard from the Quartus II software, follow
these steps:
1. On the Tools menu, click Tcl Scripts.
2. In the Tcl Scripts dialog box, under Libraries, expand the
<installation_directory>/quartus/common/tcl/apps/gui/dtw
folder, select dtw (
Figure 2–2 ).