Altera DDR Timing Wizard - Manual (Page 76)

3–16 Altera Corporation
DDR Timing Wizard User Guide November 2007
Timing Closure Process
For RLDRAM II designs created in Quartus II version 7.2 and higher, add
the Megawizard-generated <variation_name>_controller.sdc file. This
.sdc
file defines false paths between the QK signals and the PLL clock
output c0 used to read from the FIFO.
1
If the PLL clock output names used in the design are different
from the names defined in the MegaWizard-generated .sdc file,
the false path constraints are ignored. Change the PLL clock
name with the one reported in TimeQuest Timing Analyzer and
re-analyze timing again. You can check whether any constraints
are ignored by double-clicking on the Ignored Constraints
section in the TimeQuest Timing Analyzer.
Selecting Initial Phase Shifts
Memory interfaces with 2-PLL implementation have the most PLL clock
output usage. Furthermore, this implementation supports the highest
performance, so it is typically designs with 2-PLL memory interfaces that
have the most complexity to meet timing.
When using 1-PLL mode, you can use the resynchronization and
postamble clock cycles and phase shifts suggested by the legacy
controller MegaWizard as your starting point. In 2-PLL mode, however,
the legacy controller MegaWizard does not recommend any phase shifts
for the resynchronization or postamble clocks. In this case, you can use 0°
phase shift for both resynchronization clocks and 90° phase shift for the
postamble clock, as shown in
Figures 3–8 , as your starting point. Choose
these settings when instantiating the PHY for the first time.