Altera DDR Timing Wizard - Manual (Page 23)

Altera Corporation 2–11
November 2007 DDR Timing Wizard User Guide
Getting Started
1
The DTW can extract the names of PLL clocks, PLL phase
shifts, and names of registers, if you have already run the
Quartus II Analysis and Synthesis. The
auto_add_ddr_constraints.tcl
script automatically
analyzes and synthesizes the design, so you do not have to
perform Quartus II Analysis and Synthesis the first time
you invoke DTW after running the
auto_add_ddr_constraints.tcl
script. However, any time
you make a change in the PLL or the legacy controller
MegaWizard, you need to analyze and synthesize the
design before invoking DTW, so that DTW can extract the
correct clock names and phase shifts when performing an
Import function.
When the import is complete, click Skip to get to the last page of
DTW.
1
Instead of skipping to the end, you can verify the values in
the DTW by clicking Next and checking each page of the
DTW to ensure that everything is imported correctly. These
pages are described in detail in
“Manual Flow for Other
External Memory Interfaces or Source Synchronous
Systems” on page 2–14
.
At this point, if the DTW has all of the needed information, a page
similar to the one shown in
Figure 2–7 appears. Click Finish.