Altera DDR Timing Wizard - Manual (Page 74)

3–14 Altera Corporation
DDR Timing Wizard User Guide November 2007
Timing Closure Process
Timing Closure Differences in DDR2/DDR SDRAM, QDRII+/QDRII
SRAM, and RLDRAM II Interfaces
Of the three legacy memory controllers, DDR2/DDR SDRAM controllers
have the most options or settings that you can change. These controllers
are also the ones that have a more complicated timing closure process,
especially when running at high speeds.
DDR2/DDR SDRAM Interfaces
You can make changes to the DDR2/DDR SDRAM controller settings
four different ways:
■ In the DDR2/DDR SDRAM MegaWizard
■ In the altpll MegaWizard
■ In the RTL files
■ In the DTW directly
These changes are described in more detail in the later sections.
QDRII+/QDRII SRAM Interfaces
QDRII+/QDRII SRAM interfaces only uses two clocks: a system clock
and write clock, which already have default phase shifts. The
address/command clock defaults to the inverted write clock and cannot
be changed. Furthermore, QDRII+/QDRII SRAM uses a FIFO to
resynchronize the data to the system clock domain, so you do not need to
provide a resynchronization clock.
To constrain the timing between the read data and the resynchronization
registers, use the setup_relationship and hold_relationship
constraints when using Classic Timing Analyzer. For designs using
TimeQuest Timing Analyzer, convert the setup_relationship and
hold_relationship
constraints to SDC constraints manually. The
setup_relationship and hold_relationship assignment can be
directly converted to set_max_delay and set_min_delay
assignments, as shown in the following example:
set_max_delay -0.2 -from * -to <resync registers*>
set_min_delay -1.6 -from * -to <resync registers*>