Altera DDR Timing Wizard User Manual
Page 73
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Altera Corporation
3–13
November 2007
DDR Timing Wizard User Guide
Using the dtw_timing_analysis.tcl Script
Figure 3–6. Timing Closure Process
Note to
:
(1)
Depending on your design, you may need to change the RTL even after changing the clock cycle and phase shift of
the data path.
No
Compile Design
Run dtw_timing_analysis.tcl
Is the Memory Interface
Timing Met?
Change RTL (1)
Change Phase Shift in
altpll
MegaWizard
Update Clock Cycle
and/or Phase Shift
in the Legacy Controller
Megawizard
Update DTW-Only
Settings
Perform Analysis &
Synthesis
Re-Import Settings to DTW
End
Yes
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