Altera DDR Timing Wizard - Manual (Page 3)

Altera Corporation iii
November 2007
Table of Contents
About this User Guide .............................................................................. v
Revision History .................................................................................................................................... 1–v
How to Contact Altera .......................................................................................................................... 1–v
Typographic Conventions .................................................................................................................. 1–vi
Chapter 1. About the DDR Timing Wizard
Release Information ............................................................................................................................... 1–1
Device Family Support ......................................................................................................................... 1–2
Introduction ............................................................................................................................................ 1–2
Background ....................................................................................................................................... 1–2
DDR Timing Wizard ........................................................................................................................ 1–3
Features ................................................................................................................................................... 1–6
Chapter 2. Getting Started
System and Software Requirements ................................................................................................... 2–1
Design Flow ............................................................................................................................................ 2–1
Launching the DDR Timing Wizard ................................................................................................... 2–5
Entering and Editing Inputs to the DTW ........................................................................................... 2–6
Import Flow for the Altera Legacy Memory Controller IP Core or Recommended Data Path
.............................................................................................................................................................. 2–7
Manual Flow for Other External Memory Interfaces or Source Synchronous Systems ...... 2–14
The DTW Pages for DDR/DDR2 SDRAM ............................................................................ 2–14
The DTW Pages for QDRII+/QDRII SRAM & RLDRAM II ............................................... 2–45
DTW Limitations ................................................................................................................................. 2–46
Chapter 3. Using the dtw_timing_analysis.tcl Script
Introduction ............................................................................................................................................ 3–1
Running dtw_timing_analysis.tcl Script ....................................................................................... 3–3
The dtw_timing_analysis.tcl Script Results .................................................................................. 3–6
Timing Closure Process ...................................................................................................................... 3–12
Timing Closure Differences in DDR2/DDR SDRAM, QDRII+/QDRII SRAM, and RLDRAM II
Interfaces .......................................................................................................................................... 3–14
DDR2/DDR SDRAM Interfaces ............................................................................................. 3–14
QDRII+/QDRII SRAM Interfaces ........................................................................................... 3–14
RLDRAM II Interfaces .............................................................................................................. 3–15
Selecting Initial Phase Shifts ......................................................................................................... 3–16
Re-run DTW After First Compile When Using Classic Timing Analyzer ............................. 3–18
Ensure the Changes Made Outside Legacy Controller MegaWizard Are Not Erased When the
Core is Regenerated ....................................................................................................................... 3–19
Decide When to Change Clock Phase Shift ................................................................................ 3–21