Altera DDR Timing Wizard User Manual
Page 42
2–30
Altera Corporation
DDR Timing Wizard User Guide
November 2007
Entering and Editing Inputs to the DTW
with the –auto_adjust_cycles option, the DTW will have the best
clock cycle settings, so you need to update the legacy controller
MegaWizard at that point if the numbers do not match.
shows the relationship between the legacy controller
MegaWizard and the DTW, in terms of resynchronization clock
cycles and phase shifts.
Click Next.
12.
shows the DTW page for postamble clock connectivity.
The name of the PLL output driving the read postamble reset
control clock can come from the system PLL (when using 1-PLL
mode) or the fedback PLL (when using the fedback-clock mode).
Similar to the the resync_cycle field, the postamble_cycle
field is calculated by DTW when using the fedback-clock mode, but
is from the legacy controller MegaWizard when using one PLL only.
The postamble_phase is the postamble phase shift you entered in
legacy controller MegaWizard when you created the data path or
controller.
Table 2–1. Legacy Controller MegaWizard and DTW Resynchronization Clock Cycles
DTW Resynchronization
Fields
Interfaces with One PLL
(
≤ 200 MHz)
Interfaces with Fedback-Clock Mode
resync_cycle
From the Resynchronize captured read
data in cycle field in the legacy controller
MegaWizard Manual Timings tab
Calculated by DTW
resync_phase
From the Dedicated clock phase field in
the legacy controller MegaWizard Manual
Timings tab
From the Fed-back clock phase field
in the legacy controller MegaWizard
Manual Timings tab
resync_sys_cycle
Not used
From the Resynchronize captured
read data in cycle field in the legacy
controller MegaWizard Manual
Timings tab
resync_sys_phase
Not used
From the Dedicated clock phase field
in the legacy controller MegaWizard
Manual Timings tab
Note to
:
(1)
For new designs targeting memory interfaces higher than 200 MHz, Altera recommends using the
high-performance controller featuring the ALTMEMPHY megafunction in the Quartus II software.