Altera DDR Timing Wizard - Manual (Page 12)

1–6 Altera Corporation
DDR Timing Wizard User Guide November 2007
Features
Features The DDR Timing Wizard has the capability to:
■ Constrain a design with one or multiple memory controllers that
may reside in subdirectories of the main project.
■ Calculate all of the timing constraints based on your chosen FPGA or
HardCopy device, and memory device.
■ Import timing information from the legacy controller MegaWizard.
■ Enable timing driven compilation.
■ Allow the Quartus II software to analyze and report the
post-compile timing analysis for both fast and slow timing models in
one panel.
■ Create both classic timing analyzer and TimeQuest Timing Analyzer
assignments for memory interface timing paths.
The dtw_timing_analysis.tcl script complements the DTW with the
ability to:
■ Extract and report system timing margin for both fast and slow
model timing.
■ Re-run timing analysis using either the Classic Timing Analyzer or
TimeQuest Timing Analyzer.
■ Adjust resynchronization and postamble clock cycles in DTW.
■ Calculate ideal PLL phase shifts.
■ Import legacy controller MegaWizard settings into DTW (with the
option to compile the design after the import).
■ Update design t
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information in DTW.