Altera JESD204B IP - Manual (Page 107)

Parameter Description Value
F2_FRAMECLK_DIV Only applies to cases where F=2.
The divider ratio on the
frame_clk
. The deassembler always uses the
post-divided frame_clk (rxframe_clk). (34)
1, 2
RECONFIG_EN Enable reconfiguration support in the transport layer. Only
downscaling reconfiguration is supported. Disable the reconfigura‐
tion to reduce the logic.
0, 1
OUTPUT_BUS_
WIDTH
The data output bus width size that depends on the F and L.
bus_width = M*S*N
F = (M*S*N_PRIME)/(8*L)
M*S = (8*F*L)/N_PRIME
Therefore the output bus width = (8*F*L*N)/N_PRIME (8*F*L*
N)/N_
PRIME
CONTROL_BUS_
WIDTH
The control output bus width size. The width depends on the CS
parameter as well as the M and S parameters. When CS is 0, the
control data is one bit wide (tie the signal to 0).
If CS = 0, the bus width = 1. Otherwise, the bus width = (OUTPUT_
BUS_WIDTH/N*CS) while OUTPUT_BUS_WIDTH/N = M*S
OUTPU
T_BUS_
WIDTH/
N*CS
Table 5-12: Deassembler Signals
Signal Clock Domain Direction Description
Control Unit
rxlink_clk — Input
RX link clock signal. This clock is equal to the RX
data rate divided by 40. This clock is synchronous
to the
rxframe_clk
signal.
rxframe_clk — Input
RX frame clock used by the deassembler. The
frequency is a function of parameters F, F1_
FRAMECLK_DIV, F2_FRAMECLK_DIV and
rxlink_clk.
This clock is synchronous to the
rxlink_clk
signal.
rxlink_rst_n rxlink_clk Input
Reset for the RX link clock domain logic in the
deassembler. This reset is an active low signal and
the deassertion is synchronous to the rising-edge
of
rxlink_clk
.
rxframe_rst_n rxframe_clk Input
Reset for the RX frame clock domain logic in the
deassembler. This reset is an active low signal and
the deassertion is synchronous to the rising-edge
of
rxframe_clk
.
5-26 RX Path
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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