Altera JESD204B IP - Manual (Page 148)

JESD204B IP Core Debug Guidelines
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This section lists some guidelines to assist you in debugging JESD204B link issues. Apart from applying
general board level hardware troubleshooting technique like checking the power supply, external clock
source, physical damage on components, a fundamental understanding of the JESD204B subsystem
operation is important.
Related Information
• Clocking Scheme on page 7-1
• JESD204B Parameters on page 7-1
• SPI Programming on page 7-2
• Converter and FPGA Operating Conditions on page 7-2
• Signal Polarity and FPGA Pin Assignment on page 7-2
• Debugging JESD204B Link Using SignalTap II and System Console on page 7-3
Clocking Scheme
To verifying the clocking scheme, follow these steps:
1. Check that the frame and link clock frequency settings are correct in the Altera PLL IP core. For the
design example, the frame clock is assigned to outclk0 and link clock is assigned to outclk1.
2. Check the device clock frequency at the FPGA and converter.
3. For Subclass 1, check the SYSREF pulse frequency.
4. Check the clock frequency management. For the design example, using Stratix V and Arria V devices,
this frequency is 100 MHz.
JESD204B Parameters
The parameters in both the FPGA and ADC should be set to the same values. For example, when you set
K = 32 on the FPGA, set the converter's K value to 32 as well. Scrambling does not affect the link initiali‐
zation in the CGS and ILAS phases but in the user data phase. When scrambling is enabled on the ADC,
the FPGA descrambling option has to be turned on using the "Enable scramble (SCR)" option in the
JESD204B IP core Qsys parameter editor. When scrambling is enabled on the FPGA, the DAC descram‐
bling has to be turned on too.
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