Altera JESD204B IP - Manual (Page 113)

clock cycle depending on the F and FRAMECLK_DIV parameters selected based on the frame clock to
link clock relationship.
Figure 5-11: RX Data Reception
Junk
Scrambler Corrupted Data
Junk Valid Data
All 0s All 0s Valid Data
rxframe_clk
rxlink_clk
rxframe_rst_n
rxlink_rst_n
jesd204_rx_link_datain[63:0]
jesd204_rx_link_data_valid
jesd204_rx_dataout[15:0]
jesd204_rx_data_valid
Related Information
Relationship Between Frame Clock and Link Clock on page 5-9
RX Path Data Remapping
The JESD204B IP core implements the data transfer in big endian format.
The RX path data remapping is the reverse of TX path data remapping. Refer to
Figure 5-7 for the RX
transport layer remapping operation.
The following tables show examples of data mapping for L=4, F=1, 2, 4, 8 and M*S=2, 4, 8, 16. The
configurations that the transport layer support are not limited to these examples.
Table 5-13: Data Mapping for F=1, L=4
F = 1
Lane L3 L2 L1 L0
Data In {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3}
Supported
M and S
M*S=2 for F=1, L=4
F=1 supports either (case1: M=1, S=2) or (case2: M=2, S=1)
Assuming N=16, M0S0=jesd204_rx_dataout[15:0], M0S1/M1S0= jesd204_rx_dataout[31:16]
5-32 RX Path Data Remapping
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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