Altera JESD204B IP User Manual
Page 133
DATA_RADIX=BIN;
CONTENT BEGIN
0 : 00000000000000000000000000111110; -- START OF MIF
1 : 00000000000000000000000000000100;
2 : 00000000000000000000000100000001;
3 : 00000000000000000000000000000011;
.
.
.
42 : 00000000000000000000000000000010;
43 : 00000000000000000000000000001000;
44 : 00000000000000000000000001000000;
45 : 00000000000000000000000000111111; -- END OF MIF
Downscale Configuration MIF
46 : 00000000000000000000000000111110; -- START OF MIF
47 : 00000000000000000000000000000100;
48 : 00000000000000000000000100000001;
49 : 00000000000000000000000000000011;
.
.
.
88 : 00000000000000000000000000000010;
89 : 00000000000000000000000000001000;
90 : 00000000000000000000000001000000;
91 : 00000000000000000000000000111111; -- END OF MIF
END;
PHY (Stratix V and Arria V)
The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum and
downscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL and
two for channel MIF). Then, merge the files into one (phy.mif). Only the JESD204B IP cores with
maximum configuration is used in final compilation.
Maximum TX PLL Configuration MIF
WIDTH=16;
DEPTH=186;
ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;
CONTENT BEGIN
0 : 0000000000100001; -- Start of MIF opcode (TX_PLL, 6144Mbps)
1 : 0000000000100010;
.
.
.
10 : 0011000000000000;
11 : 0000000000011111; -- End of MIF opcode
Maximum Channel Configuration MIF
12 : 0000000000100001; -- Start of MIF opcode (Channel, 6144Mbps)
13 : 0000000000000010;
.
.
.
5-52
MIF ROM
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines