Altera JESD204B IP - Manual (Page 35)

Related Information
Performance and Resource Utilization on page 2-6
JESD204B IP Core Component Files
The following table describes the generated files and other files that may be in your project directory. The
names and types of generated files specified may vary depending on whether you create your design with
VHDL or Verilog HDL.
Table 3-7: Generated Files
Extension Description
<variation name>.v or .vhd IP core variation file, which defines a VHDL or Verilog HDL description of
the custom IP core. Instantiate the entity defined by this file inside of your
design. Include this file when compiling your design in the Quartus II
software.
<variation name>.cmp A VHDL component declaration file for the IP core variation. Add the
contents of this file to any VHDL architecture that instantiates the IP core.
<variation name>.sdc Contains timing constraints for your IP core variation.
<variation name>.qip Contains Quartus II project information for your IP core variation.
<variation name>.tcl Tcl script file to run in Quartus II software.
<variation name>.sip Contains IP core library mapping information required by the Quartus II
software.The Quartus II software generates a . sip file during generation of
some Altera IP cores. You must add any generated .sip file to your project
for use by NativeLink simulation and the Quartus II Archiver.
<variation name>.spd Contains a list of required simulation files for your IP core.
JESD204B IP Core Testbench
The JESD204B IP core includes a testbench to demonstrate a normal link-up sequence for the JESD204B
IP core with a supported configuration. The testbench also provides an example of how to control the
JESD204B IP core interfaces.
The testbench instantiates the JESD204B IP core in duplex mode and connects with the Altera
Transceiver PHY Reset Controller IP core. Some configurations are preset and are not programmable in
the JESD204B IP core testbench. For example, the JESD204B IP core always instantiates in duplex mode
even if RX or TX mode is selected in the JESD204B parameter editor.
Note: Dynamic reconfiguration is not supported in this JESD204B IP core testbench.
UG-01142
2015.05.04
JESD204B IP Core Component Files 3-21
Getting Started Altera Corporation
Send Feedback