Additional information, Jesd204b ip core document revision history, Additional information -1 – Altera JESD204B IP User Manual
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Additional Information
8
2015.05.04
UG-01142
Additional information about the document and Altera.
JESD204B IP Core Document Revision History
Date
Version
Changes
May 2015
2015.05.04 • Added support for Cyclone V FPGA device family.
• Updated the JESD204B IP Core Configuration values:
• M value from 1-32 to 1-256
• N' value from 4-32 to 1-32
• Updated the JESD204B IP Core FPGA Performance table.
• Updated the JESD204B IP Core FPGA Resource Utilization table.
• Added new parameters to the JESD204B IP Core Parameters table:
• Enable Capability Registers
• Set user-defined IP identifier
• Enable Control and Status Registers
• Enable Prbs Soft Accumulators
• Enable manual F configuration
• Added new topics:
•
Timing Constraints For Input Clocks
on page 3-13
•
JESD204B IP Core Deterministic Latency Implementation
on page 6-1
• Revised the note in "Simulating the IP Core Testbench" to state that
VHDL is not supported in Aldec Riviera (for Arria 10 devices only).
• Updated
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