Altera JESD204B IP - Manual (Page 34)

Frames per multiframe
(K)
1–32 Set the number of frames per multiframe. This value is
dependent on the value of F and is derived using the
following constraints:
• The value of K must fall within the range of 17/F <= K
<= min(32, floor (1024/F))
• The value of F*K must be divisible by 4
Enable scramble (SCR) On, Off Turn on this option to scramble the transmitted data or
descramble the receiving data.
Control Bits (CS) 0–3 Set the number of control bits per conversion sample.
Control Words (CF) 0–32 Set the number of control words per frame clock period
per link.
High density user data
format (HD)
On, Off Turn on this option to set the data format. This parameter
controls whether a sample may be divided over more
lanes.
• On: High Density format
• Off: Data should not cross the lane boundary
Enable Error Code
Correction (ECC_EN)
On, Off Turn on this option to enable error code correction (ECC)
for memory blocks.
Phase adjustment request
(PHADJ)
On, Off Turn on this option to specify the phase adjustment
request to the DAC.
• On: Request for phase adjustment
• Off: No phase adjustment
This parameter is valid for Subclass 2 mode only.
Adjustment resolution
step count (ADJCNT)
0–15 Set the adjustment resolution for the DAC LMFC.
This parameter is valid for Subclass 2 mode only.
Direction of adjustment
(ADJDIR)
• Advance
• Delay
Select to adjust the DAC LMFC direction.
This parameter is valid for Subclass 2 mode only.
Configurations and Status Registers Tab
Device ID
0–255 Set the device ID number.
Bank ID 0–15 Set the device bank ID number.
Lane# ID 0–31 Set the lane ID number.
Lane# checksum 0–255 Set the checksum for each lane ID.
3-20 JESD204B IP Core Parameters
UG-01142
2015.05.04
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