Altera JESD204B IP - Manual (Page 48)

The realignment rules for lane alignment are similar to frame alignment:
• If two successive and valid /A/ characters are detected at the same position other than the assumed end
of multi-frame—without receiving a valid/invalid /A/ character at the expected position between
two /A/ characters—the receiver aligns the lane to the position of the newly received /A/ characters.
• If a recent frame alignment causes the loss of lane alignment, the receiver realigns the lane frame—
which is already at the position of the first received /A/ character—at the unexpected position.
ILAS Data
The JESD204 RX IP core captures 14 octets of link configuration data that are transmitted on the 2 nd
multi-frame of the ILAS phase. The receiver waits for the reception of /Q/ character that marks the start of
link configuration data and then latch it into ILAS octets, which are per lane basis. You can read the 14
octets captured in the link configuration data through the CSR. You need to first set the
csr_ilas_data_sel
register to select which link configuration data lane it is trying to read from. Then,
proceed to read from the
csr_ilas_octet
register.
Initial Lane Synchronization
The receivers in Subclass 1 and Subclass 2 modes store data in a memory buffer (Subclass 0 mode does not
store data in the buffer but immediately releases them on the frame boundary as soon as the latest lane
arrives.). The RX IP core detects the start of multi-frame of user data per lane and then wait for the latest
lane data to arrive. The latest data is reported as RBD count (
csr_rbd_count
) value which you can read
from the status register. This is the earliest release opportunity of the data from the deskew FIFO (referred
to as RBD offset).
The JESD204 RX IP core supports RBD release at 0 offset and also provides programmable offset through
RBD count. By default, the RBD release can be programmed through the
csr_rbd_offset
to release at
the LMFC boundary. If you want to implement an early release mechanism, program it in the
csr_rbd_offset
register. The
csr_rbd_offset
and
csr_rbd_count
is a counter based on the link clock
boundary (not frame clock boundary). Therefore, the RBD release opportunity is at every four octets.
UG-01142
2015.05.04
ILAS Data 4-11
JESD204B IP Core Functional Description Altera Corporation
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