Altera JESD204B IP - Manual (Page 22)

• Set user-defined IP identifier
• Enable Control and Status Registers
• Enable Prbs Soft Accumulators
4. In the Jesd204b Configurations tab, select the following configurations:
• Common configurations (L, M, Enable manual F configuration, F, N, N', S, K)
• Advanced configurations (SCR, CS, CF, HD, ECC_EN, PHADJ, ADJCNT, ADJDIR)
5. In the Configurations and Status Registers tab, set the the following configurations:
• Device ID
• Bank ID
• Lane ID
• Lane checksum
6. After parameterizing the core, click Generate Example Design to create the simulation testbench. Skip
to step 8 if you do not want to generate the design example.
7. Set a name for your <example_design_directory> and click OK to generate supporting files and scripts.
The testbench and scripts are located in the <example_design_directory>
/ip_sim
folder.
The Generate Example Design option generates supporting files for the following entities:
• IP core for simulation—refer to
Generating and Simulating the IP Core Testbench on page 3-8
• IP core design example for simulation—refer to Generating and Simulating the Design Example
on page 5-55
• IP core design example for synthesis—refer to Compiling the JESD204B IP Core Design Example
on page 5-57
8. Click Finish or Generate HDL to generate synthesis and other optional files matching your IP
variation specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and
HDL files for synthesis and simulation.
The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove
Files in Project to manually add a
.qip or .qsys file to a project. Make appropriate pin assignments to
connect ports.
Note: Some parameter options are grayed out if they are not supported in a selected configuration or it is
a derived parameter.
Generating and Simulating the IP Core Testbench
You can simulate your JESD204B IP core variation by using the provided IP core demonstration
testbench.
To use the JESD204B IP core testbench, follow these steps:
1. Generate the simulation model. Refer to
Generating the Testbench Simulation Model on page 3-9.
2. Simulate the testbench using the simulator-specific scripts that you have generated. Refer to
Simulating the IP Core Testbench on page 3-9.
Note: Some configurations are preset and are not programmable in the JESD204B IP core testbench. For
more details, refer to JESD204B IP Core Testbench on page 3-21 or the README.txt file located
in the <example_design_directory> /ip_sim folder.
3-8 Generating and Simulating the IP Core Testbench
UG-01142
2015.05.04
Altera Corporation Getting Started
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