Altera JESD204B IP - Manual (Page 129)

Signal Clock
Domain
Direction Description
avst_usr_
dout[(FRAMECLK_
DIV*LINK*M*S*N)-1:0]
frame_
clk
Output
RX data to the Avalon-ST sink interface. The
transport layer arranges the data in a specific order,
as illustrated in the cases below:
Case 1: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M
= 1, S =1, N = 16:
• avst_usr_dout[15:0]
Case 2: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M
= 2 (denoted by m0 and m1), S =1, N = 16:
• avst_usr_dout[15:0] = m0[15:0]
• avst_usr_dout[31:16] = m1[15:0]
Case 3: If F1/F2_FRAMECLK_DIV =1, LINK = 2
(denoted by link0 and link1), M = 1, S =1, N = 16:
• avst_usr_dout[15:0] = link0
• avst_usr_dout[31:16] = link1
Case 4: If F1/F2_FRAMECLK_DIV =1, LINK = 2
(denoted by link0 and link1), M = 2 (denoted by m0
and m1), S =1, N = 16:
• avst_usr_dout[15:0] = link0, m0[15:0]
• avst_usr_dout[31:16] = link0, m1[15:0]
• avst_usr_dout[47:32] = link1, m0[15:0]
• avst_usr_dout[63:48] = link1, m1[15:0]
avst_usr_dout_valid frame_
clk
Output Indicates whether the data from the transport layer
to the Avalon-ST sink interface is valid or invalid.
• 0—data is invalid
• 1—data is valid
avst_usr_dout_ready
frame_
clk
Input Indicates that the Avalon-ST sink interface is ready
to accept data from the transport layer.
• 0—Avalon-ST sink interface is not ready to
receive data
• 1—Avalon-ST sink interface is ready to receive
data
5-48 System Interface Signals
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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