Altera JESD204B IP - Manual (Page 144)

Figure 6-5: Selecting Legal LMFC Offset Value for RX
Sequence of events in the diagram:
1. Due to trace length mismatch, SYSREF pulse arrives at the ADC first.
2. Some deterministic delay occurs in between the time when the SYSREF pulse is sampled high to the
reset of the ADC internal LMFC counter.
3. The SYSREF pulse arrives at the FPGA IP core port,
rx_sysref
, after the pulse's arrival at the ADC.
4. The FPGA IP core's internal LMFC counter resets two link clock cycles after SYSREF is sampled.
5. The LMFC phase offset between the LMFC counter at ADC and FPGA is ~3.5 link clock cycles.
6. The FPGA deasserts SYNC_N at the LMFC boundary.
7. The ADC JESD204B core detects the SYNC_N deassertion.
8. Because SYNC_N deassertion is detected after the second LMFC boundary at ADC, ILAS transmission
begins at the third LMFC boundary.
9. In this example, the ILAS arrives at the IP core's RBD elastic buffer within one local multi-frame. In
other system, the arrival at the RBD elastic buffer could span more than one local multi-frame.
Assuming csr_rbd_offset = 0, RBD elastic buffer may be released at the third or fourth LMFC boundary
due to power cycle variation.
10.Setting csr_lmfc_offset = 5 resets the LMFC counter to the value of 5.
11.The first LMFC boundary is delayed by three link clock cycles.
12.The third LMFC boundary has been delayed past the latest arrival lane power cycle variation. The RBD
elastic buffer is always released at the third LMFC boundary.
First LMFC
boundary
SYSREF pulse is
sampled by IP core
internal register
2 link clock cycle deterministic
delay from SYSREF sampled
high to the first LMFC boundary
Free running LMFC counter
Internal
LMFC Counter 0 1 2 0 1 0 1 2 3 4 5 6 7
K
SYNC_N deasserted directly
after LMFC boundary
K K K K R K K K K K
Latest arrival
lane in multiple
power cycles
D D D D
0
Power cycle
variation
Fourth LMFC
boundary
1 link clock period = LMFC count
Internal LMFC counter resets
csr_lmfc_offset=0
7
Third LMFC
boundary
D D
Free running
LMFC counter
ADC
Internal
LMFC Counter
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 7
SYSREF pulse is
sampled by ADC
SYNC_N
transmitted by RX
0
SYNC_N deassertion is detected by ADC
SYNC_N
arrival at TX
K K K K K R K K K K K L Transmit
lanes
D D D D K D D
ILAS transmission by ADC
Internal LMFC
counter resets
First LMFC
boundary
Second LMFC
boundary
Third LMFC
boundary
LMFC phase offset
R R
Free running LMFC counter
Internal
LMFC Counter 5 6 7 0 5 6 7 0 1 2 3 4 5
RBD elastic buffer released
when csr_rbd_offset=0
4
K K K K K K K K K K
Internal LMFC counter resets
csr_lmfc_offset=5
LMFC boundary is
delayed by 3 link clock
First LMFC boundary
at new location
R D D D D D D R R
1 link clock or LMFC count
to cater for power cycle variation
6
3
K
Fourth LMFC
boundary
K
Latest arrival
lane in multiple
power cycles
rx_sysref
1
2
3
4
5
6
7
8
9
10
11
12
Third LMFC boundary at new location
6-6 Programmable LMFC Offset
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Deterministic Latency Implementation Guidelines
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