Altera JESD204B IP - Manual (Page 87)

For Arria 10 devices, the only Avalon-MM operation is a direct write to the transceiver register through
the
reconfig_avmm_*
interface at the JESD204B IP core. Every line in the MIF is
DPRIO_ADDR[25:16]+ BIT_MASK[15:8]+ DATA[7:0]
. The control unit maps the
DPRIO_ADDR
to
reconfig_avmm_address
and
BIT_MASK '&' DATA
to
reconfig_avmm_data
.
Related Information
• Altera Transceiver PHY IP Core User Guide
More information about the transceiver reconfiguration controller.
• Altera Arria 10 Transceiver PHY IP Core User Guide
Transceiver Reset Controller
The transceiver reset controller uses the Altera's Transceiver PHY Reset Controller IP Core to ensure a
reliable initialization of the transceiver. The reset controller has separate reset controls per channel to
handle synchronization of reset inputs, hysteresis of PLL locked status, and automatic or manual reset
recovery mode.
In this design example, the reset controller targets both the TX and RX channels. The TX PLL, TX
Channel, and RX Channel parameters are programmable to accommodate single and multiple (2)
JESD204B links.
Related Information
• Altera Transceiver PHY IP Core User Guide
More information about the Transceiver PHY Reset Controller IP Core.
• Arria V Device Handbook, Volume 2: Transceivers
More information about the device usage mode.
Pattern Generator
The pattern generator instantiates any supported generators and has an output multiplexer to select which
generated pattern to forward to the transport layer based on the test mode during run time. Additionally,
the pattern generator also supports run-time reconfiguration (downscale) on the number of converters
per device (M) & samples per converter per frame (S).
The pattern generator can be a parallel PRBS, alternate checkerboard, or ramp wave generator. The data
output bus width of the pattern generator is equivalent to the value of FRAMECLK_DIV × M × S × N.
The pattern generator includes a REVERSE_DATA parameter to control data arrangement at the output.
The default value of this parameter is 0.
• 0—no data rearrangement at the output of the generator.
• 1—data rearrangement at the output of the generator.
For example, when M=2, S=1, N=16, F1/F2_FRAMECLK_DIV=1, the input or output data width equals
to [31:0], with the following data arrangement:
0: {m1s0[31:16], m0s0[15:0]}
1: {m0s0[31:16], m1s0[15:0]}
Parallel PRBS Generator
PRBS generator circuits often consists of simple shift registers with feedback that serve as test sources for
serial data links. The output sequence is not truly random but repeats after 2 X –1 bits, where X denotes the
5-6 Transceiver Reset Controller
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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