Altera JESD204B IP User Manual
Page 134
[88..91] : 0000000000000000;
92 : 0000000000011111; -- End of MIF opcode
Downscale TX PLL Configuration MIF
93 : 0000000000100001; -- Start of MIF opcode (TX_PLL, 3072Mbps)
94 : 0000000000100010;
.
.
.
103 : 0011000000000000;
104 : 0000000000011111; -- End of MIF opcode
Downscale Channel Configuration MIF
105 : 0000000000100001; -- Start of MIF opcode (Channel, 3072Mbps)
106 : 0000000000000010;
.
.
.
[181..184] : 0000000000000000;
185 : 0000000000011111; -- End of MIF opcode
END;
PHY (Arria 10)
The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum and
downscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL and
two for channel MIF). Then, merge the files into two (xcvr_atx_pll_combined.mif and
xcvr_cdr_combined.mif). Only the JESD204B IP cores with maximum configuration is used in final
compilation.
xcvr_atx_pll_combined.mif
Maximum Configuration MIF
CONTENT BEGIN
00 : 102FF71; -- Start of MIF
01 : 103BF01;
02 : 1047F04;
03 : 1054700;
.
.
.
10 : 11AFF00;
11 : 11CE020;
12 : 11DE020;
13 : 3FFFFFF; -- End of MIF
Downscale Channel Configuration MIF
14 : 102FF71; -- Start of MIF
15 : 103BF01;
16 : 1047F04;
17 : 1054700;
.
.
.
24 : 11AFF00;
25 : 11CE020;
26 : 11DE020;
UG-01142
2015.05.04
MIF ROM
5-53
JESD204B IP Core Design Guidelines
Altera Corporation