Altera JESD204B IP - Manual (Page 42)

• TX CSR—manages the configuration and status registers.
• TX_CTL—manages the
SYNC_N
signal, state machine that controls the data link layer states, LMFC,
and also the deterministic latency throughout the link.
• TX Scrambler and Data Link Layer—takes in 32-bits of data that implements the Initial Lane
Alignment Sequence (ILAS), performs scrambling, lane insertion and frame alignment of characters.
TX Data Link Layer
The JESD204B IP core TX data link layer includes three phases to establish a synchronized link—Code
Group Synchronization (CGS), Initial Lane Synchronization (ILAS), and User Data phase.
TX CGS
The CGS phase is achieved through the following process:
• Upon reset, the converter device (RX) issues a synchronization request by driving
SYNC_N
low. The
JESD204 TX IP core transmits a stream of /K/ = /K28.5/ symbols. The receiver synchronizes when it
receives four consecutive /K/ symbols.
• For Subclass 0, the RX converter devices deassert
SYNC_N
signal at the frame boundary. After all
receivers have deactivated their synchronization requests, the JESD204 TX IP core continues to
emit /K/ symbols until the start of the next frame. The core proceeds to transmit ILAS data sequence
or encoded user data if
csr_lane_sync_en
signal is disabled.
• For Subclass 1 and 2, the RX converter devices deassert
SYNC_N
signal at the LMFC boundary. After all
receivers deactivate the
SYNC_N
signal, the JESD204 TX IP core continues to transmit /K/ symbols until
the next LMFC boundary. At the next LMFC boundary, the JESD204B IP core transmits ILAS data
sequence. (There is no programmability to use a later LMFC boundary.)
TX ILAS
When lane alignment sequence is enabled through the
csr_lane_sync_en
register, the ILAS sequence is
transmitted after the CGS phase. The ILAS phase takes up four multi-frames. For Subclass 0 mode, you
can program the CSR (
csr_ilas_multiframe
) to extend the ILAS phase to a maximum of 256 multi-
frames before transitioning to the encoded user data phase. The ILAS data is not scrambled regardless of
whether scrambling is enabled or disabled.
The multi-frame has the following structure:
• Each multi-frame starts with a /R/ character (K28.0) and ends with a /A/ character (K28.3)
• The second multi-frame transmits the ILAS configuration data. The multi-frame starts with /R/
character (K28.0), followed by /Q/ character (K28.4), and then followed by the link configuration data,
which consists of 14 octets as illustrated in the table below. It is then padded with dummy data and
ends with /A/ character (K28.3), marking the end of multi-frame.
• Dummy octets are an 8-bit counter and is always reset when it is not in ILAS phase.
• For a configuration of more than four multi-frames, the multi-frame follows the same rule above and
is padded with dummy data in between /R/ character and /A/ character.
UG-01142
2015.05.04
TX Data Link Layer 4-5
JESD204B IP Core Functional Description Altera Corporation
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