Altera JESD204B IP - Manual (Page 137)

Note: For more information about the JESD204B design example testbench, refer to the README_DESIGN_
EXAMPLE.txt file located in the <example_design_directory> /ed_sim folder.
To run the Tcl script using the Quartus II sofware, follow these steps:
1. Launch the Quartus II software.
2. On the View menu, click Utility Windows and select Tcl Console.
3. In the Tcl Console, type
cd <example_design_directory>/ed_sim
to go to the specified
directory.
4. Type
source gen_ed_sim_verilog.tcl
(Verilog) or
source gen_ed_sim_vhdl.tcl
(VHDL) to generate the simulation files.
To run the Tcl script using the command line, follow these steps:
1. Obtain the Quartus II software resource.
2. Type
cd <example_design_directory>/ed_sim
to go to the specified directory.
3. Type
quartus_sh -t gen_ed_sim_verilog.tcl
(Verilog) or
quartus_sh -t
gen_ed_sim_vhdl.tcl
(VHDL) to generate the simulation files.
Simulating the JESD204B IP Core Design Example
By default, the Quartus II software generates simulator-specific scripts containing commands to compile,
elaborate, and simulate Altera IP models and simulation model library files. You can copy the commands
into your simulation testbench script, or edit these files to add commands for compiling, elaborating, and
simulating your design and testbench.
To simulate the design using the ModelSim-Altera SE/AE simulator, follow these steps:
1. Start the ModelSim-Altera simulator.
2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/
mentor.
3. On the File menu, click Load > Macro file. Select run_tb_top.tcl. This file compiles the design and
runs the simulation automatically, providing a pass/fail indication on completion.
To simulate the design using the VCS MX simulator (in Linux), follow these steps:
1. Start the VCS MX simulator.
2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/
synopsys/vcsmx.
3. Run run_tb_top.sh. This file compiles the design and runs the simulation automatically, providing a
pass/fail indication on completion.
To simulate the design using the Aldec Riviera-PRO simulator, follow these steps:
1. Start the Aldec Riviera-PRO simulator.
2. On the File menu, click Change Directory > Select <example_design_directory>/ed_sim/testbench/
aldec.
3. On the Tools menu, click Execute Macro. Select run_tb_top.tcl. This file compiles the design and
runs the simulation automatically, providing a pass/fail indication on completion.
Generating the Design Example For Compilation
Use the gen_quartus_synth.tcl script to generate the JESD204B design example for compilation.
Note: If you use the Quartus II Tcl console to generate the gen_quartus_synth.tcl script, close all Quartus
II project before you start generating.
5-56 Simulating the JESD204B IP Core Design Example
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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