Altera JESD204B IP - Manual (Page 109)

Signal Clock Domain Direction Description
jesd204_rx_link_
data_valid
rxlink_clk
Input
Indicates whether the
jesd204_rx_link_
datain[]
is valid or invalid.
• 0—
jesd204_rx_link_datain[]
is invalid
• 1—
jesd204_rx_link_datain[]
is valid
Connect this signal to the RX DLL
jesd204_rx_
link_valid
output pin.
jesd204_rx_link_
data_ready
rxframe_clk
Output
Indicates that the transport layer is ready to
sample
jesd204_rx_link_datain[]
.
• 0—transport layer is not ready to sample
jesd204_rx_link_datain[]
• 1—transport layer starts sampling
jesd204_
rx_link_datain[]
at the next clock cycle.
Connect this signal to the RX DLL
jesd204_rx_
link_ready
input pin.
jesd204_rx_link_
error
rxlink_clk
Output
Indicates an empty data stream due to invalid
data. This signal is asserted high to indicate an
error at the Avalon-ST sink interface (for
example, when
jesd204_rx_data_valid
= "1"
while
jesd204_rx_data_ready
= "0"). The DLL
subsequently reports this error to the CSR block.
Connect this signal to the RX DLL
jesd204_rx_
frame_error
input pin.
Signal Clock Domain Direction Description
CSR in DLL
5-28 RX Path
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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