Altera JESD204B IP - Manual (Page 88)

length of the shift register. Polynomial notation—which the polynomial order corresponds to the length
of the shift register and the period of PRBS—provides a method of describing the sequence.
Alternate Checkerboard Generator
The alternate checkerboard generator circuit consists of simple flip registers that serve as test sources for
serial data links.
The output sequence of subsequent N-bits sample is generated by inverting the previous N-bits (counting
from LSB to MSB) of the same data pattern at that clock cycle. The first N-bits sample from LSB of the
data pattern on next clock cycle is generated by inverting the last N-bits sample on the MSB of the data
pattern on current clock cycle.
Ramp Wave Generator
The ramp wave generator circuit consists of a simple register and adders that serve as test sources for
serial data links.
The output sequence of subsequent N-bits sample is an increment by one of the previous N-bits sample
(counting from LSB to MSB) in the same data pattern at that clock cycle. The first N-bits sample from LSB
of the data pattern on next clock cycle is generated by an increment by one of the last N-bits sample on
the MSB of the data pattern on current clock cycle.
Pattern Checker
The pattern checker instantiates any supported checkers and support run time reconfiguration
(downscale) of the number of converters per device (M) and samples per converter per frame (S).
The pattern checker can be either a parallel PRBS checker, alternate checkerboard checker, or ramp wave
checker. The data input bus width of the pattern checker is equivalent to the value of FRAMECLK_DIV ×
M × S × N.
The pattern checker includes an ERR_THRESHOLD parameter to control the number of error tolerance
allowed in the checker. The default value of this parameter is 1.
The pattern checker also includes a REVERSE_DATA parameter to control data arrangement at the input.
The default value of this parameter is 0.
• 0—no data rearrangement at the input of the checker.
• 1—data rearrangement at the input of the checker.
Parallel PRBS Checker
The PRBS checker contains the same polynomial as in the PRBS generator. The polynomial is only
updated when the enable signal is active, which indicates that the input data is valid. The feedback path is
XOR'ed with the input data to do a comparison. The checker flags an error when it finds any single
mismatch between polynomial data and input data.
Alternate Checkerboard Checker
The alternate checkerboard checker is implemented in the same way as in the alternate checkerboard
generator. To do a comparison, an initial seed internally generates a set of expected data pattern result to
XOR'ed with the input data. The seed is updated only when the enable signal is active, which indicates
UG-01142
2015.05.04
Alternate Checkerboard Generator 5-7
JESD204B IP Core Design Guidelines Altera Corporation
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