Altera JESD204B IP - Manual (Page 53)

Figure 4-7: Subclass 1 — Combining the
SYNC_N
Signal for JESD204B TX IP Core
SYSREF (Subclass 1)
SYSREF
SYNC_N
DEV_SYNC_N
MDEV_SYNC_N
SYSREF
SYNC_N
DEV_SYNC_N
MDEV_SYNC_N
SYSREF
SYNC_N
DEV_SYNC_N
MDEV_SYNC_N
FPGA Device
Converter Device 0
L
Converter Device 1
L
Converter Device 2
L
SYNC_N
SYNC_N
SYNC_N
Clock Chip
and SYSREF
FPGA Reference Clock
SYSREF
DAC Reference
Clock
SYSREF
JESD204B IP Core
TX
JESD204B IP Core
TX
JESD204B IP Core
TX
Related Information
Programmable RBD Offset on page 6-2
Link Reinitialization
The JESD204B TX and RX IP core support link reinitialization.
4-16 Link Reinitialization
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Functional Description
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