Altera JESD204B IP - Manual (Page 23)

Generating the Testbench Simulation Model
To generate the testbench simulation model, execute the generated script (gen_sim_verilog.tcl or
gen_sim_vhdl.tcl) located in the <example_design_directory>
/ip_sim folder.
To run the Tcl script using the Quartus II sofware, follow these steps:
1. Launch the Quartus II software.
2. On the View menu, click Utility Windows > Tcl Console.
3. In the Tcl Console, type
cd <example_design_directory>/ip_sim
to go to the specified
directory.
4. Type
source gen_sim_verilog.tcl
(Verilog) or
source gen_sim_vhdl.tcl
(VHDL)
to generate the simulation files.
To run the Tcl script using the command line, follow these steps:
1. Obtain the Quartus II software resource.
2. Type
cd <example_design_directory>/ip_sim
to go to the specified directory.
3. Type
quartus_sh -t gen_sim_verilog.tcl
(Verilog) or
quartus_sh -t
gen_sim_vhdl.tcl
(VHDL) to generate the simulation files.
Simulating the IP Core Testbench
The JESD204B IP core simulation supports the following simulators:
• ModelSim-Altera SE/AE
• VCS
• VCS MX
• Cadence
• Aldec Riviera
Note: VHDL is not supported in ModelSim-Altera AE, VCS simulators, and Aldec Riviera (for Arria 10
devices only).
Table 3-2: Simulation Setup Scripts
This table lists the simulation setup scripts and run scripts.
Simulator File Directory Script
ModelSim ® -Altera
SE/AE
<example_design_directory> /ip_sim/testbench/setup_
scripts/mentor
msim_setup.tcl
VCS <example_design_directory> /ip_sim/testbench/setup_
scripts/synopsys/vcs
vcs_setup.sh
VCS MX <example_design_directory> /ip_sim/testbench/setup_
scripts/synopsys/vcsmx
vcsmx_setup.sh
synopsys_sim.setup
Aldec Riviera <example_design_directory> /ip_sim/testbench/setup_
scripts/aldec
rivierapro_setup.tcl
Cadence <example_design_directory>
/ip_sim/testbench/setup_
scripts/cadence
ncsim_setup.sh
UG-01142
2015.05.04
Generating the Testbench Simulation Model 3-9
Getting Started Altera Corporation
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