Altera JESD204B IP - Manual (Page 57)

Clock Signal Formula Description
TX/RX PHY Clock:
txphy_clk
rxphy_clk
Data rate/40 The link clock generated from the transceiver serial
or parallel clock for the TX path or the link clock
generated from the CDR for the RX path. This clock
has the same frequency as the TX/RX link clock and
is an output from the JESD204B IP core.
There is limited use for this clock. Only if the
JESD204B configuration is F=4 and operating at
Subclass 0 mode, this clock can be used as input for
both the
txlink_clk
and
txframe_clk
, or
rxlink_
clk
and
rxframe_clk
.
TX/RX AVS Clock:
jesd204_tx_avs_clk
jesd204_rx_avs_clk
75–125 MHz The configuration clock for the JESD204B IP core
CSR through the Avalon-MM interface.
Transceiver
Management Clock:
reconfig_clk
100 MHz–125 MHz The configuration clock for the transceiver CSR
through the Avalon-MM interface. This clock is
exported only when the transceiver dynamic
reconfiguration option is enabled.
This clock is only applicable for Arria 10 devices.
Device Clock
In a converter device, the sampling clock is typically the device clock.
For the JESD204 IP core in an FPGA logic device, the device clock is used as the transceiver PLL reference
clock and also the core PLL reference clock. The available frequency depends on the PLL type, bonding
option, number of lanes, and device family. During IP core generation, the Quartus II software
recommends the available device clock frequency for the transceiver PLL based on the user selection.
Note: You need to generate the Altera PLL IP core (in Arria V and Stratix V devices) or Altera IOPLL IP
core (in Arria 10 devices) to generate the link clock and frame clock. The link clock is used in the
JESD204 IP core (MAC) and the transport layer.
Based on the JESD204B specification, the device clock is the timing reference and is source synchronous
with SYSREF. Due to the clock network architecture in the FPGA, you are recommended to use the device
clock to generate the link clock and use the link clock as timing reference.
The JESD204B protocol does not support rate matching. Therefore, you must ensure that the TX or RX
device clock (pll_ref_clk) and the PLL reference clock that generates link clock (txlink_clk or rxlink_clk)
and frame clock (txframe_clk or rxframe_clk) have 0 ppm variation. Both PLL reference clocks should
come from the same clock chip.
4-20 Device Clock
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Functional Description
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