Altera JESD204B IP - Manual (Page 46)

Figure 4-4: Receiver Data Path Block Diagram
Transceiver (RX)
Per Device
RX Frame
Deassembly
Per Device
RX CSR
Per Device
RX CTL
Per Device
Descrambler
Data Link
Layer (RX)
Soft
PCS
(RX)
Hard PCS
and
Transceiver JESD204B
(RX) Per Device
CSR
CSR
CSR
32 Bit PCS
Per Channel
32/40
PCS
SYNC_N SYSREF RX_INT RXLINK_CLK RXFRAME_CLK
Avalon-MM
Avalon-ST
To Avalon
Interface
Bus
JESD204 RX Transport Layer with
Base and Transceiver Design Example
Avalon-ST
32 Bits per Channel Serial Interface
(RX_n, RX_p)
The receiver block includes the following modules:
• RX CSR—manages the configuration and status registers.
• RX_CTL—manages the
SYNC_N
signal, state machine that controls the data link layer states, LMFC,
and also the buffer release, which is crucial for deterministic latency throughout the link.
• RX Scrambler and Data Link Layer—takes in 32-bits of data that decodes the ILAS, performs descram‐
bling, character replacement as per the JESD204B specification, and error detection (code group error,
frame and lane realignment error).
RX Data Link Layer
The JESD204B IP core RX data link layer buffers incoming user data on all lanes until the RX elastic
buffers can be released. Special character substitution are done in the TX link so that the RX link can
execute frame and lane alignment monitoring based on the JESD204B specification.
RX CGS
The CGS phase is the link up phase that monitors the detection of /K28.5/ character.
The CGS phase is achieved through the following process:
• Once the word boundary is aligned, the RX PHY layer detects the /K28.5/ 20-bit boundary and
indicate that the character is valid.
• The receiver deasserts
SYNC_N
on the next frame boundary (for Subclass 0) or on the next LMFC
boundary (for Subclass 1 and 2) after the reception of four successive /K/ characters.
• After correct reception of another four 8B/10B characters, the receiver assumes full code group
synchronization. Error detected in this state machine is the code group error. Code group error always
trigger link reinitialization through the assertion of
SYNC_N
signal and this cannot be disabled through
the CSR. The CS state machine is defined as
CS_INIT
,
CS_CHECK
, and
CS_DATA
.
• The minimum duration for a synchronization request on the
SYNC_N
is five frames plus nine octets.
Frame Synchronization
After CGS phase, the receiver assumes that the first non-/K28.5/ character marks the start of frame and
multi-frame. If the transmitter emits an initial lane alignment sequence, the first non-/K28.5/ character
UG-01142
2015.05.04
RX Data Link Layer 4-9
JESD204B IP Core Functional Description Altera Corporation
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